1. Field of the Invention
The present invention relates to a communication apparatus, and more particularly to a Global Positioning System (GPS) receiver and a correlating circuit thereof.
2. Description of the Related Art
With the rapid advancement of technology, electronic devices are being widely used in our daily life. As to a global positioning System (GPS) receiver, it becomes more and more available to use to public. For example, the navigation system installed in cars can help the drivers identify the location and direction thereof that can substantially prevent the car from being lost.
FIG. 1 is a schematic drawing of a signal frame transmitted from a satellite. The A serial represents that the satellite transmits a frame for each 30 seconds which includes 5 sub-frames and each sub-frame with 6 seconds. The B serial represents that the frame data includes the 50 bits/sec navigation data. It means that the transmission time for each bit of the navigation data is 20 ms. Prior to transmission of the navigation data and the C/A code for identifying the satellite of the C serial are performed through exclusive or logic operation for generating the D serial data. The frequency of the C/A code is 1.023 MHz which transmits 1023 bits C/A code per ms. The length of the C/A code is 1023 bits. During the transmission the data are carried by a 1575.42 MHz carrying wave for performing bi-phase shift key (BPSK) by the output from the operation of the navigation data and the C/A code as shown E serial. The modulated signals are then transmitted.
For a GPS receiver, a RF front end serves for receiving the modulated signals for the IF data, and a correlating circuit serves for searching the C/A code for identifying the satellite whose data can be received. To date, 24 satellites are orbited on six orbits. Generally, three or four satellites are sufficient to identify the location. The more the satellites are, the more precise the location will be. In addition, because of the Doppler effect, the correlating circuit refers a corrected frequency code when searching the C/A code. If the IF data received by the correlating circuit is the IF data, and the C/A code for searching the satellite is Code, and the corrected frequency code is Doppler, the correlating circuit can determine the maximum for identifying the C/A code offset and Doppler corrected frequency of the satellite whose data can be received can be expressed by the following equation:
                              ∑          0          Nms                ⁢                  IF          *          Doppler          *          Code                                    (        1        )            
The “*” represents a multiple operation, such as exclusive or logic operation, or a multiple of a single bit. “N ms” means the time period of receiving the data, which is adjustable. When the time period increases, the S/N ratio also increases which means the noise does not seriously affect. Following is a C/A code searching example, wherein the length of the C/A code is 7 bits. (Generally, the length of the C/A code is 1023 bits.)
Referring to FIG. 2, a schematic drawing of a circuit generating the 7-bit C/A code is shown. The circuit comprises a 3-bit shift register 210 and a multiplier 220. The input of the multiplier 220 is a two-bit output of the shift register 210; the output of the multiplier 220 is inputted into the shift register 210 responding to the output of the two bits. Therefore, the circuit, therefore, generates a 7-bit cycle C/A code, i.e. 1110010.
In order to search the 7-bit C/A code and determine the offset of the IF data, the correlating circuit of the GPS receiver uses the 7-bit C/A code, i.e., 1110010, and the other codes with different offset, such as 0111001, 1011100, 0101110, 0010111, 1100101, etc, to perform multiplication and addition with the IF data. The multiplication is, for example, the exclusive or logic operation shown in formula (1). If the C/A code has two-bit offset, the codes with different offset are, for example, 1110010, 0101110, 1011100, 0101110, 1001011, 1100101, etc. After the exclusive or logic operation and the addition operation, only “1011100” has a value “0”; the others have a value “4”. If “4” is deemed as the zero point of the coordinate, “0” becomes “−4” in the coordinate. After the square and radical operation, it generates the maximum “4” which can be detected by a peak detector.
Referring to FIG. 3, a waveform of a searching result of a correlating circuit is shown. In addition to the offset of the C/A code, the correlating circuit also searches the Doppler corrected frequency. The offset of the C/A code and the Doppler corrected frequency with the maximum are tracked by the satellite for acquiring the correct offset of the C/A code and the Doppler corrected frequency.
FIG. 4 is a schematic block diagram of a prior art correlating circuit. The correlating circuit includes a C/A code register 405, a Doppler corrected frequency code register 410, an I memory 415, a Q memory 420, a Doppler multiplier 425, a C/A code multiplier 430, an I analogic adder 435, a Q analogic adder 440, an I A/D converter 445, a Q A/D converter 450, a square and radical calculator 445, an integrator 460 and a peak detector 465.
The C/A code register 405 serves for storing the C/A codes to be searched. The Doppler corrected frequency code register 410 serves for storing the Doppler corrected frequency code to be searched. The I memory 415 stores the IF data received by the RF front end. The Q memory 420 stores the IF data with 90° phase shift. The I memory 415 and the Q memory 420 can store the IF data for about 20 ms for the multiplication of formula (1). The data are being processed by the Doppler multiplier 425 and the C/A code multiplier 430 for generating the multiplication of each bit. After the process of the I analogic adder 435 and the Q analogic adder 440, the addition of the multiplication of each bit is acquired. After the process of the I A/D converter 445 and the Q A/D converter 450, the digital data are acquired.
Then, after the process of the square and radical calculator 445, the absolute values of the digital data are generated. By the integration of the integrator 460, the value is then stored in the non-coherent memory 470. It can reduce the noise influence. The longer the integration time, the higher the S/N ratio. It means the noise influence is reduced. The integrated value can be detected by the peak detector 465 for acquiring correct offset of the C/A code and the Doppler corrected frequency.
The prior art correlating circuit is also disclosed in U.S. Pat. Nos. 5,896,304 and 6,009,118. The correlating circuit uses analogic adders for generating the addition of the multiplication of each bit and the total addition of the multiplication of the 1023-bit C/A code. When the process is changed, the A/D converters should be redesigned. Therefore, the process portability is degraded.
Additionally, although the correlating circuit disclosed in U.S. Pat. No. 6,383,046 can improve the process portability, it processes the C/A code bits sequentially and then in parallel and does not have the buffer of the IF data. Therefore, it cannot perform the operation in parallel.